The present invention relates to a semiconductor device having a plurality of semiconductor chips which are three-dimensionally laminated one upon another.
These years, there has been spotlighted to a technology of system packages in which several semiconductor chips incorporated therein integrated circuits are densely packaged, and which have a high performance, and accordingly, several firms have proposed several various packaging configurations. In particular, there have been prosperously developed laminated packages in which several semiconductor chips are three-dimensionally packaged so as to be allow the packages to be comparatively small-sized.
Since wire-bonding is in general utilized for electrical connection between a substrate and a semiconductor chip mounted thereon, it is required that the sizes of the semiconductor chips to be laminated one upon another are set, the higher the laminated stage, the smaller the size of the semiconductor chip. Accordingly, in order to laminate semiconductor chips having substantially equal sizes, spacers should be interposed therebetween so as to ensure areas for wire-bonding. The connection of the wire-bonding has a high degree of freedom of wiring lay-out, and accordingly, is extremely effective for practical electrical connection for a plurality of existing semiconductor chips in a short TAT (Turn Around Time).
However, the wire-bonding connection requires such a process that all wirings from a plurality of electrodes of semiconductor chips are once led onto a mounting substrate, and thereafter, rewiring is made for one of the chips. Thus, there have been raised a problem of a long wiring length between the chips, and a problem of an extremely high wiring density on the mounting substrate. Thus, an inductance between chips is increased, and accordingly, high speed transmission becomes difficult. Further, the high wiring density on the mounting substrate causes a lower yield, resulting in an increase in the costs of the mounting substrate. Thus, there may be raised not only such a problem that an inductance between the chips increases so as to cause difficulty in high speed transmission and but also such a problem that the higher density of the mounting substrate deteriorates the yield so as to increase the substrate costs.
In view of the above-mentioned problems caused by the wire bonding connection, there has bee proposed a method for carrying out connection between chips with no intervention of a mounting substrate. As disclosed in JP-A-2001-217385, there has been proposed such a method that semiconductor chips are applied thereto with wiring tapes which are tape carrier-like and which have wiring layers with predetermined patterns, at their upper and lower surfaces and at their one side surface, these surfaces being incorporated thereto with external connection terminals, so as to form a package structure capable of connecting the upper and lower chips laminated one upon anther, therebetween. Although this method is a conventionally known package lamination type one in which chips individually packaged are connected by means of external electrodes, three dimensional lamination can be made having a size substantially equal to that of the chip by improving this conventional method. However, due to a laminated structure in which individual packages are laminated one upon another, there have been raised such problems that a wiring length becomes longer between chips, and that the freedom in the case of lamination of different kinds of chips having different sizes has to be limited.
On the contrary, as disclosed in JP-A-11-251316 and JP-A-2000-260934, there have been proposed such methods that electrodes are formed in chips, piercing therethrough so as to connect between upper and lower chips. JP-A-11-251316 discloses a process of manufacturing a semiconductor device using, for example, copper wirings, in which copper piercing electrodes are also formed, so as to provide a semiconductor chip with piercing electrodes that can greatly simplify the manufacturing process. The JP-A-2000-260934 discloses such a method that electrodes which are formed by embedding solder or low melting point metal in through-holes in a chip by electroplating or electroless plating at upper and lower parts of the chips, and the chips are heated, after they are laminated one upon another, so as to melt and fuse the embedded electrodes in order to three-dimensionally connect the chips with one another.
As stated above, the method using wire bonding has been in general used as a method of tree-dimensionally laminating a plurality of semiconductor chips for packaging. However, there will be caused in future such a problem that the wiring length causes a bottle neck problem in view of high speed transmission and miniaturization and thinning of the package in view of ensuring its bonding area. Thus, as a method instead thereof, there has been proposed a three-dimensional connection between chips by shortest wirings using piercing electrodes. Since a process of forming piercing electrodes in a silicon substrate is a novel one which has not yet been used in a wafer process or a mounting process, there have been required, as a premise of introduction thereof, a low process load, a short TAT, simple connection, and such reliability as has been conventionally available.
The process of manufacturing a devise, as disclosed in the JP-A-11-251316, in which copper piercing electrodes are simultaneously formed, is effective for reducing the process load, but reference dimensions between a devise manufacturing process and a mounting process are different from each other by not less than two figures. Accordingly, should the piercing electrodes to be used for connection between chips by a mounting process, be formed also in the devise manufacturing process, there would be caused problems of lowering a yield and a TAT as to the manufacture of devices.
Further, as disclosed in JP-A-2000-260934, in a method in which bump electrodes are formed in through holes in chips through plating growth, there would be raised a problem of taking a relatively long time for the plating growth (several hours) and a problem of incurring technical difficulty in uniform plating growth including through-holes having a high aspect ratio.
Further, different from a method using wire bonding, semiconductor chips which are laminated on the upper stage side are not directly connected to external electrodes through the intermediary of mounting substrates. Accordingly, it is required to manifest a process of wiring between upper and lower chips, which enables operation of the upper stage side semiconductor chip. For example, with such a structure that different kinds of semiconductor chips are laminated one upon another, operating voltages are possibly different from one another. Further, with a multi-stage lamination structure of the same kind of chips, there would be caused a problem of chip select for the upper stage semiconductor chip.